82375EB Datasheet, PDF (16/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Pin Name
C BE 3 0
FRAME
TRDY
IRDY
STOP
PLOCK
Type
Description
t s BUS COMMAND AND BYTE ENABLES The command and byte enable signals are
multiplexed on the same PCI pins During the address phase of a transaction
C BE 3 0 define the bus command for bus command definitions During the data
phase C BE 3 0 are used as Byte Enables The Byte Enables determine which
byte lanes carry meaningful data C BE 0 applies to byte 0 and C BE 3 to byte
3 C BE 3 0 are not used for address decoding
The PCEB drives C BE 3 0 as an initiator of a PCI Bus cycle and monitors
C BE 3 0 as a target
When PCIRST is asserted the PCEB drives C BE 3 0 to keep them from
floating In addition the PCEB acts as the central resource responsible for driving the
C BE 3 0 signals when no device owns the PCI Bus and the bus is idle
sts
FRAME FRAME is driven by the current initiator to indicate the beginning and
duration of an access FRAME is asserted to indicate that a bus transaction is
beginning During a transaction data transfers continue while FRAME is asserted
When FRAME is negated the transaction is in the final data phase FRAME is an
input when the PCEB is the target FRAME is an output when the PCEB is the
initiator During reset this signal is tri-stated
sts
TARGET READY TRDY as an output indicates the target’s ability to complete
the current data phase of the transaction TRDY is used in conjunction with
IRDY A data phase is completed on any clock that both TRDY and IRDY are
sampled asserted When PCEB is the target during a read cycle TRDY indicates
that the PCEB has valid data present on AD 31 0 During a write it indicates that the
PCEB as a target is prepared to latch data TRDY is an input to the PCEB when
the PCEB is the initiator During reset this signal is tri-stated
sts
INITIATOR READY IRDY as an output indicates the initiator’s ability to complete
the current data phase of the transaction IRDY is used in conjunction with
TRDY A data phase is completed on any clock that both IRDY and TRDY are
sampled asserted When PCEB is the initiator of a write cycle IRDY indicates that
the PCEB has valid data present on AD 31 0 During a read it indicates the PCEB is
prepared to latch data IRDY is an input to the PCEB when the PCEB is the target
During reset this signal is tri-stated
sts
STOP As a target the PCEB asserts STOP to request that the master stop the
current transaction When the PCEB is an initiator STOP is an input As an initiator
the PCEB stops the current transaction when STOP is asserted Different
semantics of the STOP signal are defined in the context of other handshake
signals (TRDY and DEVSEL ) During reset this signal is tri-stated
sts
PCI LOCK PLOCK indicates an atomic operation that may require multiple
transactions to complete PLOCK is an input when PCEB is the target and output
when PCEB is the initiator When PLOCK is sampled negated during the address
phase of a transaction a PCI agent acting as a target will consider itself a locked
resource until it samples PLOCK and FRAME negated When other masters
attempt accesses to the PCEB (practically to the EISA subsystem) while the PCEB is
locked the PCEB responds with a retry termination During reset this signal is tri-
stated
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