82375EB Datasheet, PDF (104/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
The ESC negates CMD after one BCLK period unless the slave adds wait states (negates EXRDY) The ESC
latches SD 15 0 into the PCEB’s data swap buffer on the trailing edge of CMD The ESC controls the PCEB
data swap buffers via the PCEB ESC Interface The ESC then asserts START and presents BE 3 0 (upper
word enabled) The ESC negates START and asserts CMD The slave latches the address on the trailing
edge of START and presents data on SD 15 0 The ESC negates CMD after one BCLK unless the slave
negates EXRDY The ESC latches SD 15 0 into the PCEB data swap buffers on the trailing edge of CMD
and instructs the PCEB data swap buffer to copy D 15 0 to D 31 0 and asserts EX32 Note that since the
transfer is intended for the PCEB the data is not re-driven back out onto the EISA Bus The ESC floats the
START and BE 3 0 The PCEB regains control of the EISA Bus after sampling EX32 and EX16
asserted
PCEB Writing To a 16-bit EISA Slave
As a 32-bit EISA master the PCEB begins by placing the address on LA 31 2 and driving M IO The 16-bit
EISA slave decodes the address and asserts EX16 The PCEB asserts START W R BE 3 0 and
SD 31 0 The ESC samples EX32 and EX16 on the rising edge of BCLK following the assertion of
START and asserts CMD At the same time the PCEB negates START and samples EX32 When
EX32 is sampled negated the PCEB floats START SD 31 0 and BE 3 0 The data is latched in the
PCEB’s data swap buffers Note that the PCEB continues to drive a valid address on LA 31 2
The ESC instructs the PCEB to drive the data out on SD 31 0 and asserts CMD after sampling EX32
negated The slave may sample SD 15 0 while CMD is asserted The ESC negates CMD after one BCLK
unless the slave adds wait states (negates EXRDY) The ESC then presents BE 3 0 (upper word enabled)
and asserts START The ESC instructs the PCEB to copy SD 31 0 to SD 15 0 negates START and
asserts CMD The ESC negates CMD after one BCLK unless the slave negates EXRDY The slave
latches the address on the trailing edge of START and samples SD 15 0 on the trailing edge of CMD The
ESC returns control of the EISA Bus to the PCEB by floating BE 3 0 and START then asserting EX32
The PCEB samples EX32 and EX16 asserted on the rising edge of BCLK
104