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| 82375EB Datasheet, PDF (88/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB) | |||
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82375EB SB
Table 6 Fixed Priority Mode Bank Control Bits (Continued)
Mode
Bank
Priority
3 2b 2a 1 0 Highest
x 1 1 xx
Reserved
10 1 0 0 0 0 PCEBREQ REQ0
REQ2
REQ1
CPUREQ
11 1 0 0 0 1 REQ0
PCEBREQ
REQ2
REQ1
CPUREQ
12 1 0 0 1 0 PCEBREQ REQ0
REQ2
REQ1
REQ3
13 1 0 0 1 1 REQ0
PCEBREQ
REQ2
REQ1
REQ3
14 1 0 1 0 0 CPUREQ
REQ3
PCEBREQ REQ0
15 1 0 1 0 1 CPUREQ
REQ3
REQ0
PCEBREQ
16 1 0 1 1 0 REQ3
CPUREQ
PCEBREQ REQ0
17 1 0 1 1 1 REQ3
CPUREQ
REQ0
PCEBREQ
18 1 1 0 0 0 REQ2
REQ1
19 1 1 0 0 1 REQ2
REQ1
1A 1 1 0 1 0 REQ2
REQ1
1B 1 1 0 1 1 REQ2
REQ1
x 1 1 xx
CPUREQ
CPUREQ
REQ3
REQ3
REQ3
PCEBREQ
REQ3
REQ0
CPUREQ
PCEBREQ
CPUREQ
REQ0
Reserved
Lowest
REQ3
REQ3
CPUREQ
CPUREQ
REQ2
REQ1
REQ1
REQ2
REQ2
REQ1
REQ2
REQ1
REQ0
PCEBREQ
REQ0
PCEBREQ
Note that these two tables are permutations of the same table with different value of the Bank 3 fixed priority
control bit The fixed bank control bit(s) selects which requester is the highest priority device within that
particular bank Bits 7 4 must be programmed to all 0âs (rotate mode disabled) to get these combinations The
selectable fixed priority schemes provide 24 of the 128 possible fixed mode permutations possible for the six
masters
88
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