82375EB Datasheet, PDF (67/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
5 1 2 6 Memory Write
Target support
Decode
Negative (82374SB only) and Subtractive
Data Path Flow through
PCEB Response
Memory write cycles may be claimed by the PCEB via negative or subtractive decoding The PCEB asserts
DEVSEL to claim the cycle Unclaimed PCI cycles (DEVSEL time-out) within the 4 GByte memory space
are claimed by the PCEB via subtractively decoding and forwarded to the EISA Bus The memory write cycle is
subject to retry If the PCEB is locked the cycle triggers buffer management activity If the EISA Bus is
occupied by an EISA ISA master or the DMA the memory write cycle is retried If the cycle is retried due to a
disabled buffer because the EISA Bus is occupied the EISA Bus is requested
Once a memory write cycle is accepted (not retried) by the PCEB the PCEB holds the PCI Bus in wait states
(using TRDY ) until the cycle is completed on the EISA Bus
Result of no response on EISA The PCEB initiates a standard length EISA memory write cycle and terminates
normally
Initiator support
Data Path Line Buffer when enabled flow through when Line Buffer is disabled
Cycle Generation Conditions
As an initiator the PCEB generates a PCI memory write cycle when it decodes an EISA memory write cycle
destined to PCI that can not be serviced by the Line Buffer because it is disabled This occurs for EISA ISA
masters and DMA cycles when the Line Buffer is disabled The PCEB also generates a memory write cycle
when the Line Buffer needs to be flushed The Line Buffer is flushed under several conditions including when
the 16 byte line is full when there is a ‘‘miss’’ to the current 16 byte line or when it is required by the buffer
management logic (See Section 6 0 Data Buffering)
As an initiator the PCEB generates only linear incrementing burst ordering that is signaled by AD 1 0 ^e‘‘00’’
during address phase Other types of burst transfers (i e cache line toggle mode) are never initiated by the
PCEB
Result of no response on PCI Master abort due to DEVSEL time-out
5 1 2 7 Configuration Read Configuration Write
Target support
Decode
via IDSEL pin
Data Path Flow through
Response
The PCEB responds to configuration cycles by generating DEVSEL when its IDSEL signal is asserted
regardless of the address During configuration cycles AD 7 2 are used to address the PCEB’s configuration
space AD 31 8 are not used and are logical ‘‘don’t cares’’ AD 1 0 must be zero
Result of no response on EISA N A
Initiator support
Configuration cycles are never generated by the PCEB
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