82375EB Datasheet, PDF (39/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
3 1 16 IORT ISA I O RECOVERY TIMER REGISTER
Address Offset
Default Value
Attribute
Size
4Ch
56
Read Write
8 bits
The I O recovery logic is used to guarantee a minimum amount of time between back-to-back 8-bit and 16-bit
PCI-to-ISA I O slave accesses These minimum times are programmable
The I O recovery mechanism in the PCEB is used to add recovery delay between PCI-originated 8-bit and 16-
bit I O cycles to ISA devices The delay is measured from the rising edge of the EISA command signal
(CMD ) to the falling edge of the next EISA command The delay is equal to the number of EISA Bus clocks
(BCLKs) that correspond to the value contained in bits 1 0 for 16-bit I O devices and in bits 5 3 for 8-bit I O
devices Note that no additional delay is inserted for back-to-back I O ‘‘sub-cycles’’ generated as a result of
byte assembly or disassembly This register defaults to 8- and 16-bit recovery enabled with two clocks of I O
recovery
Bit
Description
7 Reserved
6 Bit I O Recovery Enable This bit enables the recovery times programmed into bits 0 and 1 of this
register When this bit is set to 1 the recovery times shown for bits 5-3 are enabled When this bit is set
to 0 recovery times are disabled
5 3 8-Bit I O Recovery times This 3-bit field defines the recovery times for 8-bit I O Programmable
delays between back-to-back 8-bit PCI cycles to ISA I O slaves is shown in terms of EISA clock cycles
(BCLK) The selected delay programmed into this field is enabled disabled via bit 6 of this register
Bits 5 3
001
010
011
100
101
110
111
000
BCLK
1
2
3
4
5
6
7
8
2 16-Bit I O Recovery Enable This bit enables the recovery times programmed into bits 0 and 1 of this
register When this bit is set to 1 the recovery times shown for bits 0 and 1 are enabled When this bit
is set to 0 recovery times are disabled
1 0 16-Bit I O Recovery Times This 2-bit field defines the Recovery time for 16-bit I O Programmable
delays between back-to-back 16-bit PCI cycles to ISA I O slaves is shown in terms of EISA clock
cycles (BCLK) The selected delay programmed into this field is enabled disabled via bit 2 of this
register
Bits 1 0 B
01
10
11
00
CLK
1
2
3
4
39