82375EB Datasheet, PDF (58/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Address
(hex)
01F4h
01F5h
01F6h
01F7h
0376h
0377h
03F6h
03F7h
FEDC
0000
0000
0000
0000
0000
0000
0000
0000
Table 4 EISA Resident IDE Registers (Continued)
Addess (Bits)
BA98 7654
3210
Access
Type
Register Name
0001 1111 0100
RW
Primary Cylinder Low Register
0001 1111 0101
RW
Primary Cylinder High Register
0001 1111 0110
RW
Primary Drive head Register
0001 1111 0111
RW
Primary Status Register
0011 0111 0110
RW
Secondary Alternate Status Register
0011 0111 0111
R
Secondary Drive Address Register
0011 1111 0110
RW
Primary Alternate Status Register
0011 1111 0111 R
Primary Drive Address Register
4 2 EISA Cycle Address Decoding
For EISA Bus cycles the PCEB address decoder determines the destination of EISA ISA master and DMA
cycles This decoder provides the following functions
 Positively decodes memory and I O addresses that have been programmed into the PCEB for forwarding
to the PCI Bus This includes accesses to devices that reside directly on the PCI (memory Regions 4 1
and I O Regions 4 1 ) and segments of main memory that resides behind the Host PCI Bridge
 Provides access attributes for memory Regions 4 1 These attributes are used to select the most optimum
access mode (buffered or non-buffered)
 All cycles that are not positively decoded to be forwarded to PCI are contained within EISA
NOTE
The registers that reside in the PCEB (configuration registers and BIOS Timer) are not accessible
from the EISA Bus
4 2 1 POSITIVELY DECODED MEMORY CYCLES TO MAIN MEMORY
The EISA ISA master or DMA addresses that are positively decoded by the PCEB are forwarded to the PCI
Bus If the address is not positively decoded by the PCEB the cycle is not forwarded to the PCI Bus Subtrac-
tive and negative (82374SB only) decoding are not used on the EISA Bus
The PCEB permits several EISA memory address ranges (items a-i) to be positively decoded EISA Bus cycles
to these regions are forwarded to the PCI Bus Regions described by a-f and h are fixed and can be enabled or
disabled independently These regions are controlled by the EADC1 and EADC2 Registers
The region described by g defines a space starting at 1 MByte with a programmable upper boundary of
4 GByte - 2 MByte Within this region a hole can be opened Its size and location are programmable to allow a
hole to be opened in memory space (for a frame buffer on the EISA Bus for example) The size of this region
and the hole are controlled by the MCSTOM MCSBOH and MCSTOH Registers If a hole in main memory is
defined then accesses to that address range are contained within EISA unless defined by the EISA-to-PCI
memory regions as a PCI destined access (See next section )
58