82375EB Datasheet, PDF (107/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
290477 – 71
Figure 27 EISA Memory and I O Read Write Cycles (One Extended and Two Standard Cycles)
7 2 2 EISA MEMORY BURST CYCLES
The EISA burst cycles permit a continuous sequence of read or write cycles in zero wait-states (1 BCLK per
transfer) A burst transfer is either all reads or all writes Mixed cycles are not allowed As an EISA slave the
PCEB supports burst memory reads and burst memory writes from to its Line Buffers Figure 28 shows an
example of a burst sequence for both memory reads and writes on the EISA Bus During the particular burst
sequence five data transfers occur with a wait state added on the third data transfer
The first transfer in a burst transfer begins like the standard cycle described above The EISA master presents
a valid address on LA 31 2 The PCEB after decoding the address and M IO responds by asserting
SLBURST The EISA master must sample SLBURST on the rising edge of BCLK at the trailing edge of
START The EISA master asserts MSBURST on the falling edge of BCLK and presents a second address
to the PCEB The ESC holds CMD asserted while the burst is being performed If MSBURST is not
asserted by the master the cycle is run as a standard cycle
If the cycle is a burst read the EISA master presents burst addresses on the falling edge of every BCLK The
PCEB presents the data for that address which is sampled one and half BCLKs later If the cycle is a burst
write the EISA master presents the data on the rising edge of BCLK a half cycle after presenting the address
The PCEB samples memory write data on the rising BCLK edge when CMD is asserted (regardless of the
state of MSBURST ) The EISA master terminates the burst cycles by negating MSBURST and completing
the last transfer
107