82375EB Datasheet, PDF (108/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
To add wait states during a burst sequence the PCEB negates EXRDY before the falling edge of BCLK (with
CMD asserted) The EISA master samples EXRDY on the falling edge of BCLK and extends the cycle until
EXRDY is asserted The EISA master can still change the next address even though EXRDY is negated
Figure 28 EISA Burst Cycle
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7 3 I O Recovery
The I O recovery mechanism in the PCEB guarantees a minimum amount of time between back-to-back 8-bit
and 16-bit PCI cycles to ISA I O slaves Delay times (in BCLKs) for 8-bit and 16-bit cycles are individually
programmed via the IORT Register Accesses to an 8-bit device followed by an access to a 16-bit device use
the 8-bit recovery time Similarly accesses to a 16-bit device followed by an access to an 8-bit device use the
16-bit recovery time The PCEB cycles to EISA I O DMA cycles and EISA ISA bus masters to I O slaves do
not require any delay between back-to-back I O accesses
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