82375EB Datasheet, PDF (63/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
NOTE
1 All signals are sampled on the rising edge of the PCI clock Each signal has a setup and hold
window with respect to the rising clock edge in which transitions are not allowed Outside of this
range signal values or transitions have no significance
2 The terms initiator and master are synonymous Likewise the terms target and slave are synony-
mous
3 Readers should be familiar with the PCI Bus specification
5 1 PCI Bus Transactions
This section presents the PCI Bus transactions supported by the PCEB
5 1 1 PCI COMMAND SET
PCI Bus commands indicate to the target the type of transaction requested by the master These commands
are encoded on the C BE 3 0 lines during the address phase of a transfer Table 5 summarizes the PCEB’s
support of the PCI Bus commands
C BE 3 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 5 PCEB-Supported PCI Bus Commands
Command Type
Supported As Target
Interrupt Acknowledge
Yes
Special Cycle
No
I O Read
Yes
I O Write
Yes
Reserved
N A⁽³⁾
Reserved
N A⁽³⁾
Memory Read
Yes
Memory Write
Yes
Reserved
N A⁽³⁾
Reserved
N A⁽³⁾
Configuration Read
Yes
Configuration Write
Yes
Memory Read Multiple
No⁽²⁾
Reserved
N A⁽³⁾
Memory Read Line
No⁽²⁾
Memory Write and Invalidate
No⁽¹⁾
Supported As Initiator
No
No
Yes
Yes
N A⁽³⁾
N A⁽³⁾
Yes
Yes
N A⁽³⁾
N A⁽³⁾
No
No
No
N A⁽³⁾
No
No
NOTES
1 As a target the PCEB treats this command as a memory write command
2 As a target the PCEB treats this command as a a memory read command
3 The PCEB considers a reserved command invalid and as a target completely ignores the transaction All internal ad-
dress decoding is ignored and the PCEB never asserts DEVSEL As a PCI master the PCEB never generates a bus
cycle with a reserved command type
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