82375EB Datasheet, PDF (21/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Pin Name
EXRDY
EX32
EX16
MSBURST
Type
Description
od EISA READY EXRDY is used by EISA I O and memory slaves to request wait
states during a cycle Each wait state is a BCLK period
The PCEB as an EISA master or slave samples EXRDY As an input the EXRDY is
sampled on the falling edge of BCLK after the CMD has been asserted and if
inactive each falling edge thereafter
When PCEB is an EISA slave it may drive EXRDY low to introduce wait states
During reset this signal is not driven
od EISA 32 BIT EX32 is used by the EISA slaves to indicate support of 32 bit
transfers When the PCEB is an EISA master it samples EX32 on the same rising
edge of BCLK that START is negated
During mismatched cycles (see note at the end of this section) EX32 (and EX16 )
is used to transfer the control back to the PCEB EX32 (along with EX16 ) is
asserted by the ESC on the falling edge of BCLK before the rising edge of the BCLK
when the last CMD is negated This indicates that the cycle control is transferred
back to the PCEB
As an EISA slave the PCEB always drives EX32 to indicate 32 bit support for EISA
cycles During reset this signal is not driven
in
EISA 16 BIT EX16 is used by the EISA slaves to indicate their support of 16 bit
transfers As an EISA master the PCEB samples EX16 on the same rising edge of
BCLK that START is negated
During mismatched cycles (see note at the end of this section) EX16 (and EX32 )
is used to transfer the control back to the PCEB EX16 (along with EX32 ) is
asserted by the ESC on the falling edge of the BCLK before the rising edge of the
BCLK when the last CMD is negated This indicates that the cycle control is
transferred back to the PCEB
As an EISA slave the PCEB never asserts EX16
t s MASTER BURST MSBURST is an output when the PCEB is an EISA master and
an input when the PCEB is a slave
As a master the PCEB asserts MSBURST to indicate to the slave that the next
cycle is a burst cycle If the PCEB samples SLBURST asserted on the rising edge
of BCLK after START is asserted the PCEB asserts MSBURST on the next
BCLK edge and proceeds with the burst cycle
As a slave the PCEB monitors this signal in response to the PCEB asserting
SLBURST The EISA master asserts MSBURST to the PCEB to indicate that the
next cycle is a burst cycle As a slave the PCEB samples MSBURST on the rising
edge of BCLK after the rising edge of BCLK that CMD is asserted by the ESC
MSBURST is sampled on all subsequent rising edges of BCLK until the signal is
sampled negated The burst cycle is terminated on the rising edge of BCLK when
MSBURST is sampled negated unless EXRDY is sampled negated on the
previous falling edge of BCLK During reset this signal is tri-stated
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