82375EB Datasheet, PDF (42/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Bit
Description
7
0EC000 – 0EFFFFh BIOS Extension WE 1^eEnable 0^eDisable
6
0EC000 – 0EFFFFh BIOS Extension RE 1^eEnable 0^eDisable
5
0E8000 – 0EBFFFh BIOS Extension WE 1^eEnable 0^eDisable
4
0E8000 – 0EBFFFh BIOS Extension RE 1^eEnable 0^eDisable
3
0E4000 – 0E7FFFh BIOS Extension WE 1^eEnable 0^eDisable
2
0E4000 – 0E7FFFh BIOS Extension RE 1^eEnable 0^eDisable
1
0E0000 – 0E3FFFh BIOS Extension WE 1^eEnable 0^eDisable
0
0E0000 – 0E3FFFh BIOS Extension RE 1^eEnable 0^eDisable
3 1 20 PDCON PCI DECODE CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
58h
00h
Read Write
8 bits
This register enables disables positive decode of PCI accesses to the IDE and 8259 locations residing in the
expansion bus subsystem For the 82374SB this register controls the mode of address decode (subtractive or
negative) for memory cycles on the PCI Bus
Subtractive decoding
PCI memory cycles that are not claimed on the PCI Bus (i e DEVSEL inactive) are forwarded to the EISA
Bus This is the default on power up
Negative decoding (82374SB Only)
PCI memory cycles that are not mapped to one of the regions defined by A B or C below are immediately
forwarded to the EISA Bus (i e without waiting for DEVSEL time-out) PCI memory cycles that are decoded
to one of the four programmable PCI memory regions but are not claimed (DEVSEL negated) are forwarded
to the EISA Bus by subtractive decode
A Main memory locations defined by the MEMCS mapping (MCSCON MCSBOH MCSTOH MCSTOM
MAR1 MAR2 and MAR3 Registers)
B The enabled Video Frame Buffer region 0A0000 – 0BFFFFh (as indicated by bit 2 of the EADC1 Register)
C The four programmable PCI memory regions (defined by the MEMREGN 4 1 registers)
NOTE
If there are devices on the PCI that are not mapped into any of the regions defined by A B or C
then negative decoding can not be used
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