82375EB Datasheet, PDF (34/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Bit
Description
7 Auto-PEREQ Control (APC) APC Enables Disables control of the auto-PEREQ function when
GAT mode is enabled via bit 0 (GAT^e1) When APC^e1 (and GAT^e1) the PEREQ signal is
asserted whenever the EISAHLDA signal is asserted When APC^e0 the PEREQ signal is not
automatically asserted but it will be activated upon PCI Bus request from any PCI agent After
PCIRST APC^e1 (enabled) See note
6 5 Reserved
4 3 Master Retry Timer (MRT) This 2-bit field determines the number of PCICLKs after the first retry that
a PCI initiator’s bus request will be masked Note that for proper system operation this register must
be programmed with either 01 10 11
Bits 4 3
00
01
10
11
Operation
Timer disabled Retries never masked (Default)
Retries unmasked after 16 PCICLK’s
Retries unmasked after 32 PCICLK’s
Retries unmasked after 64 PCICLK’s
2 Bus Park (BP) When BP^e1 the PCEB will park CPUREQ on the PCI Bus when it detects the PCI
Bus idle If BP^e0 the PCEB takes responsibility for driving AD C BE and PAR signals upon
detection of bus idle state After PCIRST BP^e0 (disabled)
1 Bus Lock (BL) When BL^e1 Bus Lock is enabled The arbiter considers the entire PCI Bus locked
upon initiation of any LOCKed transaction When BL^e0 Resource Lock is enabled A LOCKed agent
is considered a LOCKed resource and other agents may continue normal PCI transactions After
PCIRST BL^e0 (disabled)
0 Guaranteed Access Time (GAT) When GAT^e1 the PCEB is configured for Guaranteed Access
Time mode This mode guarantees the 2 1 ms CHRDY time-out specification for the EISA ISA Bus
When the PCEB is a PCI initiator on behalf of an EISA ISA master the PCI and main memory bus
(host) are arbitrated for in serial and must be owned before the EISA ISA master is given ownership of
the EISA Bus If the PCEB is not programmed for Guaranteed Access Time (GAT^e0) the EISA ISA
master is first granted the EISA Bus before the PCI Bus is arbitrated After a PCIRST GAT^e0
(disabled)
3 1 9 ARBPRI PCI ARBITER PRIORITY CONTROL REGISTER
Address Offset
Default Value
Attribute
Size
42h
04h
Read Write
8 bits
This register controls the operating modes of the PCEB’s internal PCI arbiter The arbiter consists of four
arbitration banks that support up to six masters and three arbitration priority modesfixed priority rotating
priority and mixed priority modes See Section 5 4 PCI Bus Arbitration for details on programming and using
different arbitration modes
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