82375EB Datasheet, PDF (66/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Result of no response on EISA
The PCEB runs a standard length EISA I O cycle and terminates normally
Initiator support
The PCEB generates PCI I O write cycles on behalf of an EISA master EISA cycles are forwarded to the PCI
Bus if the I O address is within one of the four programmable I O address regions defined in Section 4 0
Address Decoding
Result of no response on PCI
Master abort due to DEVSEL time-out
5 1 2 5 Memory Read
Target support
Decode
Negative (82374SB only) and Subtractive
Data Path Flow through
PCEB Response
Memory read cycles may be claimed by the PCEB via negative or subtractive decoding The PCEB claims the
cycle by asserting DEVSEL Unclaimed PCI cycles (DEVSEL time-out) are claimed by the PCEB via
subtractively decoding and forwarded to the EISA Bus The memory read cycle is subject to retry If the PCEB
is locked if the cycle triggers buffer management activity or if the EISA Bus is occupied by an EISA ISA
master or the DMA the memory read cycle is retried If the cycle is retried due to an occupied EISA Bus the
EISA Bus is requested
Once a memory read cycle is accepted (not retried) by the PCEB the PCI Bus is held in wait states using
TRDY until the cycle is completed to the EISA Bus
Incremental burst memory reads destined for the EISA Bus take longer than the allowed 8 PCICLKs There-
fore any burst memory read cycle decoded by the PCEB causes the PCEB to target terminate the cycle after
the first data transaction using the disconnect semantics of the STOP signal (Figure 5-8 Disconnect A)
Result of no response on EISA
The PCEB runs a standard length EISA memory read cycle and terminates normally
Initiator support
Data Path Line Buffer when enabled Flow through when Line Buffer is disabled or it is a bypass cycle
Cycle Generation Conditions
As an initiator the PCEB generates a PCI memory read cycle when it decodes an EISA memory read cycle
destined to the PCI that can not be serviced by the Line Buffer This condition occurs for EISA ISA master and
DMA cycles that can not be serviced by the Line Buffer because the Line Buffer is empty there is a Line Buffer
miss or Line Buffering is disabled
As an initiator the PCEB only generates linear incrementing burst ordering that is signaled by AD 1 0 ^e 00
during the address phase Other types of burst transfers (i e cache line toggle mode) are never initiated by the
PCEB
The PCEB generates a burst memory read when it is fetching 16 bytes into one of the four Line Buffers
Result of no response on PCI
Master abort due to DEVSEL time-out PCEB returns data value FFFFFFFFh
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