82375EB Datasheet, PDF (22/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Pin Name
SLBURST
LOCK
BE 3 0
LA 31 24
LA 23 2
Type
Description
t s SLAVE BURST SLBURST is an input when the PCEB is an EISA master and an
output when the PCEB is a slave
When the PCEB is a master the slave indicates that it supports burst cycles by
asserting SLBURST to the PCEB The PCEB samples SLBURST on the rising
edge of BCLK at the end of START for EISA master cycles
When the PCEB is an EISA slave this signal is an output As a slave the PCEB
asserts this signal to the master indicating that the PCEB supports EISA burst cycles
During reset this signal is tri-stated
t s LOCK When asserted LOCK guarantees exclusive memory access This signal is
asserted by the PCEB when the PCI master is running locked cycles to EISA slaves
When asserted this signal locks the EISA subsystem
LOCK can also be activated by a device on the EISA Bus This condition is
propagated to the PCI Bus via the PLOCK signal During reset this signal is tri-
stated
t s BYTE ENABLES BE 3 0 identify the specific bytes that are valid during the
current EISA Bus cycles When the PCEB is an EISA master and the cycles are
directed to a matched slave (slave supports 32-bit transfers) the BE 3 0 are
outputs from the PCEB
When the cycles are directed to a mis-matched slave (slave does not support 32-bit
transfers - see note) the BE 3 0 are floated one and half BCLKs after START is
asserted These signals become inputs (driven by the ESC) for the rest of the cycle
BE 3 0 are pipelined signals and must be latched by the addressed slave When
the PCEB is an EISA ISA DMA slave BE 3 0 are inputs to the PCEB
Upon PCIRST these signals are tri-stated and placed in output mode
t s LATCHABLE ADDRESS LA 31 24 and LA 23 2 are the EISA address signals
When the PCEB is an EISA master these signals are outputs from the PCEB These
addresses are pipelined and must be latched by the EISA slave LA 31 24 and
LA 23 2 are valid on the falling edge of START Note that the upper address bits
are inverted before being driven on LA 31 24 The timing for LA 31 24 and
LA 23 2 are the same
When the PCEB is an EISA slave these signals are inputs and are latched by the
PCEB
For I O cycles the PCEB as an EISA master floats LA 31 24 to allow for ESC’s
address multiplexing (during I O cycle to configuration RAM) LA 23 2 are actively
driven by the PCEB For memory cycles the PCEB as an EISA master drives the LA
address lines During reset these signals are tri-stated
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