82375EB Datasheet, PDF (51/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
5 Positively decodes memory addresses for selected regions of main memory (located behind the Host PCI
Bridge) When a main memory address is positively decoded the PCEB asserts the MEMCS signal to the
Host PCI Bridge The PCEB does not assert DEVSEL
6 Subtractively or negatively (82375SB only) decodes cycles to the EISA Bus (see Section 4 1 1 Memory
Space Address Decoding)
NOTE
A PCI requirement is that upon power-up PCI agents do not respond to any address Typically the
only access to a PCI agent is through the IDSEL configuration mechanism until the agent is enabled
during initialization The PCEB ESC subsystem is an exception to this since it controls access to the
BIOS boot code The PCEB subtractively decodes BIOS accesses and passes the accesses to the
EISA Bus where the ESC generates BIOS chip select This allows BIOS memory to be located in the
PCI memory space
4 1 1 MEMORY SPACE ADDRESS DECODING
The MCSCON MCSTOP MCSBOH MCSTOM and PDCON Registers are used to program the decoding for
PCI Bus memory cycles
4 1 1 1 Main Memory Decoding (MEMCS )
The PCEB supports positive decode of main memory areas by generating a memory chip select signal
(MEMCS ) to the Host PCI Bridge that contains the main memory interface control The PCEB supports
memory sizes up to 512 MBytes (i e the PCEB can be programmed to generate MEMCS for this memory
range) For PCI memory accesses above 512 MByte (512 MBytes to 4 GBytes) the PCEB does not generate
MEMCS and unclaimed cycles are forwarded to the EISA Bus using either subtractive or negative (82374SB
only) decoding
If a memory region is enabled accesses to that region are positively decoded and result in the PCEB asserting
MEMCS If a memory region is disabled accesses do not generate MEMCS and the cycle is either
subtractively or negatively (82374SB only) decoded and forwarded to the EISA Bus
Within the 512 MByte main memory range the PCEB supports the enabling disabling of sixteen individual
memory ranges (Figure 3) Fourteen of the ranges are within the 640 KByte - 1 MByte area and have Read
Enable (RE) and Write Enable (WE) attributes These attributes permit positive address decoding for reads
and writes to be independently enabled disabled This permits for example an address range to be positively
decoded for a memory read and subtractively or negatively (82374SB only) decoded to the EISA Bus for a
memory write
The fifteenth range (0–512 KByte) and sixteenth range (programmable limit address from 2 MByte up to
512 MByte on 2 MByte increments) can be enabled or disabled but do not have RE WE attributes A seven-
teenth range is available that identifies a memory hole Addresses within this hole will not generate a
MEMCS These memory address ranges are
 0–512 KByte
 512–640 KByte
 640–768 KBytes (VGA memory page)
 960 KByte to 1 MByte (BIOS Area)
 768–896 KByte in 16 KByte segments (total of 8 segments)
 896–960 KByte in 16 KByte segments (total of 4 segments)
 960 KByte to 1 MByte (Upper BIOS area)
 1–512 MByte in 2 MByte increments
 Programmable memory hole in 64 KByte increments between 1 MByte and 16 MByte
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