82375EB Datasheet, PDF (5/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

CONTENTS
5 1 2 9 Memory Read Line
5 1 2 10 Memory Write And Invalidate
5 1 3 PCI TRANSFER BASICS
5 1 3 1 Turn-Around-Cycle Definition
5 1 3 2 Idle Cycle Definition
5 1 4 BASIC READ
5 1 5 BASIC WRITE
5 1 6 CONFIGURATION CYCLES
5 1 7 INTERRUPT ACKNOWLEDGE CYCLE
5 1 8 EXCLUSIVE ACCESS
5 1 9 DEVICE SELECTION
5 1 10 TRANSACTION TERMINATION
5 1 10 1 Master Initiated Termination
5 1 10 2 Target Initiated Termination
5 1 10 3 PCEB Target Termination Conditions
5 1 10 4 PCEB Master Termination Conditions
5 1 10 5 PCEB Responses Results Of Termination
5 1 11 PCI DATA TRANSFERS WITH SPECIFIC BYTE ENABLE COMBINATIONS
5 2 PCI Bus Latency
5 2 1 MASTER LATENCY TIMER (MLT)
5 2 2 INCREMENTAL LATENCY MECHANISM
5 3 PCI Bus Parity Support And Error Reporting
5 3 1 PARITY GENERATION AND CHECKING
5 3 1 1 Address Phase
5 3 1 2 Data Phase
5 3 2 PARITY ERROR PERR SIGNAL
5 3 3 SYSTEM ERRORS
5 4 PCI Bus Arbitration
5 4 1 PCI ARBITER CONFIGURATION
5 4 1 1 Fixed Priority Mode
5 4 1 2 Rotating Priority Mode
5 4 1 3 Mixed Priority Mode
5 4 1 4 Locking Masters
5 4 2 ARBITRATION SIGNALING PROTOCOL
5 4 2 1 REQ and GNT Rules
5 4 2 2 Back-to-Back Transactions
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