82375EB Datasheet, PDF (78/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Figure 16 Device Selection (DEVSEL )
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5 1 10 TRANSACTION TERMINATION
Termination of a PCI cycle can be initiated by either a master or a target The PCEB supports both master and
target initiated termination All transactions are concluded when FRAME and IRDY are both sampled
negated indicating that the PCI Bus is idle
5 1 10 1 Master Initiated Termination
The PCEB supports three types of master initiated termination
 Completion Refers to the termination when the PCEB finishes the transaction normally This is the most
common type of termination
 Time-out Refers to termination when the PCEB’s GNT line is negated and its internal Master Latency
Timer has expired The intended transaction is not necessarily concluded The timer may have expired
because of a target-induced access latency or because the intended operation was very long
 Abort Refers to termination when there is no target response (no DEVSEL asserted) to a transaction
within the programmed DEVSEL response time
Completions and time-outs are common while the abort is an abnormal termination A normal termination of
this type can be seen in Section 5 1 4 and 5 1 5 in the descriptions of the basic PCI read and write transaction
The PCEB sends out a master abort (Figure 17) when the target does not respond to the PCEB-initiated
transaction by asserting DEVSEL The PCEB checks DEVSEL based on the programmed DEVSEL
sample point If DEVSEL is not asserted by the programmed sample point the PCEB aborts the transaction
by negating FRAME and then one clock later negating IRDY The master abort condition is abnormal and
it indicates an error condition The PCEB does not retry the cycle
If the transaction is an EISA-to-PCI memory or I O write the PCEB terminates the EISA cycle with EXRDY If
the transaction is an EISA-to-PCI memory or I O read the PCEB returns FFFFFFFFh on the EISA Bus This is
identical to the way an unclaimed cycle is handled on the ‘‘normally ready’’ EISA Bus If the Line Buffer is the
requester of the PCI transaction the master abort mechanism ends the PCI cycle but no data is transferred
into or out of the Line Buffer The Line Buffer does not retry the cycle The Received Master Abort Status bit in
the PCI Status Register is set to 1 indicating that the PCEB issued a master abort
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