82375EB Datasheet, PDF (83/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
5 2 2 INCREMENTAL LATENCY MECHANISM
As a target the PCEB supports the Incremental Latency Mechanism for PCI-to-EISA cycles The PCI specifi-
cation states that for multi-data phase PCI cycles if the incremental latency from current data phase (N) to the
next data phase (N^a1) is greater than eight PCICLKs the target must manipulate TRDY and STOP to
stop the transaction after the current data phase (N) All PCI-to-EISA cycles (memory read write and I O read
write) are automatically terminated (during a burst) after the first data phase because they require more than
eight PCICLKs to complete on the EISA Bus
Therefore the PCEB does not need to specifically implement an 8 PCICLK timer and the PCEB handles a
disconnect in a pre-determined fashion based on the type of current transaction
5 3 PCI Bus Parity Support And Error Reporting
PCI provides for parity and asynchronous system errors to be detected and reported separately The PCEB
ESC chip set implements both mechanisms The PCEB implements only parity generation and checking and it
does not interface to the SERR signal Reporting of both PERR and SERR indicated errors is implement-
ed in the ESC
5 3 1 PARITY GENERATION AND CHECKING
The PCEB supports parity generation and checking on the PCI Bus During the address and data phases
parity covers AD 31 0 and the C BE 3 0 lines regardless of whether or not all lines carry meaningful
information Byte lanes that are not actually transferring data are still required to be driven with stable (albeit
meaningless) data and are included in the parity calculation Parity is calculated such that the number of 1s on
AD 31 0 C BE 3 0 and the PAR signals is an even number
The role of the PCEB in parity generation checking depends on the phase of the cycle (address or data) the
type of bus cycle (read or write) and whether the PCEB is a master or target The following paragraphs and
Figure 20 summarize the behavior of the PCEB during the address and data phase of a PCI Bus cycle
Figure 20 Parity Operation
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