82375EB Datasheet, PDF (31/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
3 1 4 PCISTS PCI STATUS REGISTER
Address Offset
Default Value
Attribute
Size
06 – 07h
0200h
Read Only Read Write Clear
16 bits
This 16-bit register provides status information for PCI Bus-related events Some bits are read write clear
These bits are set to 0 whenever the register is written and the data in the corresponding bit location is 1 (R
WC) For example to clear bit 12 and not affect any other bits write the value 0001 0000 0000 0000b to
this register Note that for certain PCI functions that are not implemented in the PCEB the control bits are still
shown (labeled ‘‘not supported’’)
Bit
Description
15 Parity Error Status (PERRS) R WC This bit is set to 1 whenever the PCEB detects a parity error
even if parity error handling is disabled (as controlled by bit 6 in the PCI Command Register)
Software sets PERRS to 0 by writing a 1 to this bit location
14 SERR Status (SERRS) Not Supported This bit is used to indicate that a PCI device asserted the
SERR signal The PCEB does not implement this signal SERRS is always read as 0
13 Master Abort Status (MA) R WC When the PCEB as a master generates a master abort this bit
is set to 1 Software sets MA to 0 by writing a 1 to this bit location
12 Received Target Abort Status (RTAS) R WC When the PCEB as a master receives a target
abort condition this bit is set to 1 Software sets RTAS to 0 by writing a 1 to this bit location
11 Signaled Target Abort Status (STAS) Not Supported This bit is set to 1 by a PCI target device
when they generate a Target Abort Since the PCEB never generates a target abort this bit is not
implemented and will always be read as a 0
10 9 DEVSEL Timing Status (DEVT) RO This read only field indicates the timing of the DEVSEL
signal when PCEB responds as a target The PCI Specification defines three allowable timings for
assertion of DEVSEL 00b^efast 01b^emedium and 10b^eslow (11b is reserved) DEVT indicates
the slowest time that a device asserts DEVSEL for any bus command except configuration read
and configuration write cycles The PCEB implements medium speed DEVSEL timing and
therefore DEVT 10 9 ^e01 when read
8 0 Reserved
3 1 5 RID REVISION IDENTIFICATION REGISTER
Address Offset 08h
Default Value
03h (82375EB A-2 stepping)
04h (82375SB B-0 stepping)
Attribute
Size
Read Only
8 bits
This 8-bit register contains the device revision number of the PCEB Writes to this register have no effect
Bit
Description
7 0 Revision Identification Number This 8-bit value is the revision number of the PCEB
31