82375EB Datasheet, PDF (56/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Negative decoding has the following properties
 All addresses above the top of main memory or within the MEMCS hole (as defined by the MEMCS
map) are negatively decoded to EISA except for the four programmable EISA-to-PCI memory regions
These regions (MEMREGN 4 1 ) can overlap with active main memory ranges the main memory hole or
with the memory space above the top of main memory PCI accesses to MEMREGN 4 1 are always
subtractively decoded to EISA
 All addresses within MEMCS defined ranges 640 KByte to 1 MByte can be either mapped to PCI or EISA
using positive decoding Some of these regions allow more detailed mapping based on programmable
access attributes (read enable and write enable) This permits a region to be positively decoded for the
enabled attribute and negatively decoded if enabled to the EISA Bus for the disabled attribute For exam-
ple if a region is enabled for reads and disabled for writes accesses to the region are positively decoded to
the PCI for reads and negatively decoded if enabled to EISA for writes If negative decoding is disabled
(i e subtractive decoding enabled) the write is subtractively decoded to EISA
 When negative decoding is enabled MEMREGN 4 1 can still be set up for subtractive decoding A PCI
device that requires subtractive decoding must reside within Region 4 1 As a result the subtractive
decoding penalty is only associated with some address ranges (i e some devices) and not with all non-PCI
ranges This feature can be used with PCI devices that dynamically change response on PCI cycles based
on cycle type or an internal device state (e g intervention cycle)
If a PCI device can not be located in one of the regions (Region 4 1 ) then negative decoding can not be
used This could occur for systems with very specific address mapping requirements or systems where the
device addresses that reside on the PCI Bus are highly fragmented and could not be accommodated with
four regions
Note that the four regions do not limit mapping to only four devices More than one device can be mapped
into the same programmable region These devices will reside within their own sub-regions which are not
necessarily contiguous
4 1 2 PCEB CONFIGURATION REGISTERS
PCI accesses to the PCEB configuration registers are positively decoded For a detailed address map of the
PCEB configuration registers see Section 3 1 Configuration Registers
4 1 3 PCEB I O REGISTERS
The only I O-mapped register in the PCEB is the BIOS Timer Register Section 3 2 provides details on the
address mapping of this register Note that the internal decode of the BIOS Timer Register is disabled after
reset and all I O accesses that are not contained within the PCI are subtractively decoded and passed to EISA
Bus To enable I O access to the PCEB’s BIOS Timer Register The BTMR Register must be programmed
4 1 4 POSITIVELY DECODED COMPATIBILITY I O REGISTERS
The 8259 interrupt controller and IDE register locations are positively decoded Access to the corresponding
I O address ranges must first be enabled through the PDCON Register
PCI accesses to these registers are broadcast to the EISA Bus These PCI accesses require the ownership of
the EISA Bus and will be retried if the EISA Bus is owned by an EISA ISA master or the DMA
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