82375EB Datasheet, PDF (46/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
3 1 24 IOREGN 4 1 EISA-TO-PCI I O REGION ADDRESS REGISTERS
Address Offset
Default value
Attribute
Size
70-73h (I O Region 1)
74-77h (I O Region 2)
78-7Bh (I O Region 3)
7C-7Fh (I O Region 4)
0000FFFCh
Read Write
32 bits
These 32-bit registers provide four windows for EISA-to-PCI I O accesses The windows define positively
decoded programmable address regions for mapping EISA I O space to the corresponding PCI I O space
Each register determines the starting and limit addresses of the particular region within the 64 KByte PCI I O
space The base and limit addresses can be aligned on any Dword boundary and each region can be sized in
Dword increments (32-bits) up to the theoretical maximum size of 64 KByte Default values for the base and
limit fields ensure that the regions are initially disabled
The I O regions are selected based on the following formula Base Address ^s address ^s Limit Address
Bit
Description
31 18 I O Region Limit Address For EISA-to-PCI I O accesses bits 31 18 correspond to address lines
LA 15 2 on the EISA Bus and AD 15 2 on the PCI Bus This field determines the limit address of
the region within the 64 KByte PCI I O space
17 16 Reserved
15 2 I O Region Base Address For EISA-to-PCI I O accesses bits 15 2 correspond to address lines
LA 15 2 on the EISA Bus and AD 15 2 on the PCI Bus This field determines the starting address
of the region within the 65 KByte PCI I O space
1 0 Reserved
3 1 25 BTMR BIOS TIMER BASE ADDRESS REGISTER
Address Offset
Default value
Attribute
Size
80 – 81h
0078h
Read Write
16 bits
This 16-bit register determines the base address for the BIOS Timer Register located in PCI I O space The
BIOS Timer resides in the PCEB and is the only internal resource mapped to PCI I O space The base address
can be set at Dword boundaries anywhere in the 64 KByte PCI I O space This register also provides the BIOS
Timer access enable disable control bit
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