82375EB Datasheet, PDF (28/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Address
Offset
00 – 01h
02 – 03h
04 – 05h
06 – 07h
08h
09 – 0Ch
0Dh
0E – 3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48 – 49h
4A – 4Bh
4Ch
4Dh – 53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
Table 1 Configuration Registers
Abbreviation
Register Name
VID
DID
PCICMD
PCISTS
RID
MLTIM
PCICON
ARBCON
ARBPRI
ARBPRIX
MCSCON
MCSBOH
MCSTOH
MCSTOM
EADC1
IORTC
MAR1
MAR2
MAR3
PDCON
EADC2
Vendor Identification
Device Identification
Command Register
Status Register
Revision Identification
Reserved
Master Latency Timer
Reserved
PCI Control
PCI Arbiter Control
PCI Arbiter Priority Control
PCI Arbiter Priority Control Extension
MEMCS Control
MEMCS Bottom of Hole
MEMCS Top of Hole
MEMCS Top of Memory
EISA Address Decode Control 1
Reserved
ISA I O Recovery Time Control
Reserved
MEMCS Attribute Register 1
MEMCS Attribute Register 2
MEMCS Attribute Register 3
Reserved
PCI Decode Control
Reserved
EISA Address Decode Control 2
Reserved
Access
RO
RO
RW
RO R WC
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
28