82375EB Datasheet, PDF (36/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Bit
Description
7 5 Reserved
4 MEMCS Master Enable When bit 4^e1 the PCEB asserts MEMCS for all accesses to the defined
MEMCS region (as defined by the MCSTOM Register and excluding the memory hole defined by the
MCSBOH and MCSTOH Registers) if the accessed location is in a region enabled by bits 3 0 of this
register or in the regions defined by the MAR1 MAR2 and MAR3 registers When bit 4^e0 the entire
MEMCS function is disabled and MEMCS is never asserted
3 Write Enable For 0F0000 – 0FFFFFh (Upper 64 KByte BIOS) When bit 3^e1 the PCEB generates
MEMCS for PCI master memory write accesses to the address range 0F0000 – 0FFFFFh When bit
3^e0 the PCEB does not generate MEMCS for PCI master memory write accesses to the address
range 0F0000–0FFFFFh
2 Read Enable For 0F0000 – 0FFFFFh (Upper 64 KByte BIOS) When bit 2^e1 the PCEB generates
MEMCS for PCI master memory read accesses to the address range 0F0000 – 0FFFFFh When bit
2^e0 the PCEB does not generate MEMCS for PCI master memory read accesses to the address
range 0F0000–0FFFFFh
1 Write Enable For 080000 – 09FFFFh (512 – 640 KByte) When bit 1^e1 the PCEB generates
MEMCS for PCI master memory write accesses to the address range 080000 – 09FFFFh When bit
1^e0 the PCEB does not generate MEMCS for PCI master memory write accesses to the address
range 080000–09FFFFh
0 Read Enable For 080000 – 09FFFFh (512 – 640 KByte) When bit 0^e1 the PCEB generates
MEMCS for PCI master memory read accesses to the address range 080000 – 09FFFFh When bit
0^e0 the PCEB does not generate MEMCS for PCI master memory read accesses to the address
range 080000–09FFFFh
3 1 12 MCSBOH MEMCS BOTTOM OF HOLE REGISTER
Address Offset
Default value
Attribute
Size
45h
10h
Read Write
8 bits
This register defines the bottom of the MEMCS hole MEMCS is not generated for accesses to addresses
within the hole defined by this register and the MCSTOH Register The hole is defined by the following
equation
TOH ^t address ^t BOH TOH is the top of the MEMCS hole defined by the MCSTOH Register and BOH is
the bottom of the MEMCS hole defined by this register
For example to program the BOH at 1 MByte the value of 10h should be written to this register To program
the BOH at 2 MByte ^a 64 KByte this register should be programmed to 21h To program the BOH at 8 MByte
this register should be programmed to 80h
When the TOH ^k BOH the hole is disabled If TOH^eBOH the hole size is 64 KBytes It is the responsibility of
the programmer to guarantee that the BOH is at or above 1 MB AD 31 24 must be 0’s for the hole meaning
the hole is restricted to be under the 16 MByte boundary The default value for the BOH and TOH disables the
hole
Bit
Description
7 0 Bottom of MEMCS Hole Bits 7 0 correspond to address lines AD 23 16 respectively
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