82375EB Datasheet, PDF (30/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
3 1 3 PCICMD PCI COMMAND REGISTER
Address Offset
Default Value
Attribute
Size
04 – 05h
0007h
Read Write Read Only
16 bits
This 16-bit register contains PCI interface control information This register enables disables PCI parity error
checking enables disables PCEB bus master capability and enables disables the PCEB to respond to PCI-
originated memory and I O cycles Note that for certain PCI functions that are not implemented within the
PCEB the control bits are still shown (labeled ‘‘not supported’’)
Bit
Description
15 9 Reserved
8 SERR Enable (SERRE) Not Supported RO Function of this bit is to control the SERR signal
Since the PCEB does not implement the SERR signal this bit always reads as 0 (disabled)
7 Wait State Control (WSC) Not Supported RO This bit controls insertion of wait-states for
devices that do not meet the 33-10 PCI specification Since PCEB meets the 33-10 specification this
control function is not implemented WSC is always read as 0
6 Parity Error Enable (PERRE) R W PERRE controls the PCEB’s response to PCI parity errors
When PERRE^e1 the PCEB asserts the PERR signal when a parity error is detected When
PERRE^e0 the PCEB ignores any parity errors that it detects After PCIRST PERRE^e0 (parity
checking disabled)
5 VGA Palette Snoop (VGPS) Not Supported RO This bit is intended only for specific control of
PCI-based VGA devices and it is not applicable to the PCEB This bit is not implemented and always
reads as 0
4 Memory Write and Invalidate Enable (MWIE) Not Supported RO This is an enable bit for using
the Memory Write and Invalidate command The PCEB doesn’t support this command as a master
As a slave the PCEB aliases this command to a memory write This bit always reads as 0 (disabled)
3 Special Cycle Enable (SCE) Not Supported RO Since this capability is not implemented the
PCEB does not respond to any type of special cycle This bit always reads as 0
2 Bus Master Enable (BME) R W ME enables disables the PCEB’s PCI Bus master capability
When BME^e0 the PCEB bus master capability is disabled This prevents the PCEB from requesting
the PCI Bus on behalf of EISA ISA masters the DMA or the Line Buffers When BME^e1 the bus
master capability is enabled This bit is set to 1 after PCIRST
1 Memory Space Enable (MSE) R W This bit enables the PCEB to accept PCI-originated memory
cycles When MSE^e1 the PCEB responds to PCI-originated memory cycles to the EISA Bus When
MSE^e0 the PCEB does not respond to PCI-originated memory cycles to the EISA Bus (DEVSEL is
inhibited) This bit is set to 1 (enabled for BIOS access) after PCIRST
0 I O Space Enable (IOSE) R W This bit enables the PCEB to accept PCI-originated I O cycles
When IOSE^e1 the PCEB responds to PCI-originated I O cycles When IOSE^e0 the PCEB does
not respond to a PCI I O cycle (DEVSEL is inhibited) including I O cycles bound for the EISA Bus
This bit is set to 1 (I O space enabled) after PCIRST
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