82375EB Datasheet, PDF (72/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
5 1 5 BASIC WRITE
Figure 9 shows the PCEB as a master writing to PCI memory in zero wait states Figure 10 shows the fastest
response of the PCEB as a target to a memory or I O write transaction generated by a PCI master
As a PCI master the PCEB performs memory write and I O transfers If buffering of memory accesses is
enabled write transfers are posted When writing data to PCI memory the PCEB writes a maximum of 16
bytes (one line of the Line Buffer) using a burst write cycle I O writes are always non-buffered transactions
The PCEB generates PCI write cycles on behalf of EISA masters and DMA devices and when the PCEB
flushes its internal Line Buffer
As a PCI target the PCEB responds to both I O and memory write transfers If the EISA Bus is occupied the
PCI write is retried by the PCEB When the PCEB owns the EISA Bus the transaction proceeds For burst I O
writes the PCEB always target terminates after the first data transaction by asserting STOP and TRDY at
the end of the first data phase During a burst memory write the PCEB always target terminates after the first
data phase
Figure 10 shows the fastest PCEB response to a write cycle targeted to an internal PCI configuration register
During I O or memory write accesses to the EISA Bus the PCEB always adds wait states The PCEB adds
wait states by holding TRDY high until the transfer on the EISA Bus is completed
Figure 9 PCEB Write to PCI Memory
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