82375EB Datasheet, PDF(43/131 Page) Intel Corporation

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82375EB Datasheet, PDF (43/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

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82375EB SB

Bit

Description

7 6 Reserved

5 8259 Decode Control (8259DC) This bit enables disables positive decode of 8259 locations 0020h

0021h 00A0h and 00A1h When this bit is 1 positive decode for these locations are enabled When

this bit is 0 positive decode for these locations is disabled After reset this bit is 0 Note that if positive

decode is disabled these 8259 locations can still be accessed via subtractive decode

4 IDE Decode Control (IDEDC) This bit enables disables positive decode of IDE locations 1F0 â 1F7h

(primary) or 170â177h (secondary) and 3F6h 3F7h (primary) or 376h 377h (secondary) When

IDEDCe0 positive decode is disabled When IDECDe1 positive decode is enabled After reset this

bit is 0 Note that if positive decode is disabled these IDE locations can still be accessed via

subtractive decode

3 1 Reserved

0 82375EB Reserved Must be 0 when programming this register

82375SB PCI Memory Address Decoding Mode (PMAD) This bit selects between subtractive and

negative decoding When PMADe1 negative decoding is selected When PMADe0 subtractive

decoding is selected After reset this bit is 0

3 1 21 EADC2 EISA ADDRESS DECODE CONTROL EXTENSION REGISTER

Address Offset

Default value

Attribute

Size

5Ah

00h

Read Write

8 bits

This register specifies EISA-to-PCI mapping for the 896 KByte to 1 MByte memory address range (BIOS) If

this memory block is enabled EISA memory accesses in this range will result in the EISA cycles being

forwarded to the PCI Bus (Note that enabling this block is necessary if BIOS resides within the PCI and not

within the EISA subsystem )

This register also defines mapping for the 16 MByte - 64 KByte to 16 MByte memory address range This

mapping is important if the BIOS is aliased at the top 64 KBytes of 16 MBytes If the region is enabled and this

address range is within the hole defined by the MCSBOH and MCSTOH Registers or above the top of main

memory defined by the MCSTOM Register the EISA cycle is forwarded to the PCI

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