82375EB Datasheet, PDF (84/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
5 3 1 1 Address Phase
As a master the PCEB drives AD 31 0 and C BE 3 0 and calculates the corresponding parity value and
drives it on the PAR signal 1 clock later As a target the PCEB does not check parity during the address
phase of a bus cycle
5 3 1 2 Data Phase
As a master during a write cycle the PCEB drives AD 31 0 and C BE 3 0
ing parity value and drives it on the PAR signal 1 clock later
and calculates the correspond-
As a master during a read cycle the PCEB only drives C BE 3 0 The responding target drives AD 31 0
lines (data) and calculates parity based on the received C BE 3 0 and outgoing AD 31 0 signals The
target drives PAR during the following clock The PCEB calculates parity based on the outgoing C BE 3 0
and the incoming AD 31 0 signals at the end of the data phase It compares it with the incoming value of the
PAR signal and asserts PERR if there is no match
As a target during a write cycle the PCEB calculates parity on the incoming AD 31 0 and C BE 3 0 signals
and compares the result on the next clock with the incoming value on the PAR signal If the value does not
match the PCEB asserts PERR
As a target during a read cycle the PCEB calculates parity on the incoming C BE 3 0 and outgoing
AD 31 0 signals The PCEB drives the calculated parity value during the next clock The master of the
transaction receives the data calculates parity on its outgoing C BE 3 0 and incoming AD 31 0 signals
and compares its calculated value on the next clock with the parity value on the PAR signal (supplied by the
PCEB) If the values do not match the master asserts PERR
5 3 2 PARITY ERROR PERR SIGNAL
When the PCEB is involved in a bus transaction (master or target) it asserts the PERR signal if enabled via
the PCICMD Register to indicate a parity error for the bus cycle PERR is a sustained tri-state (s t s) type of
signal (see Section 2 0 Signal Description) Note that PCI parity errors signaled by PERR are reported to
the host processor via the ESC’s system interrupt control logic When the PCEB detects a parity error during
one of its bus transactions it sets the parity error status bit in the PCI Status Register regardless of whether
the PERR signal is enabled via the PCICMD Register
5 3 3 SYSTEM ERRORS
The PCEB does not generate system errors (SERR ) Thus the PCEB does not have the capability of
indicating parity errors during the address phase in which it is a potential target (i e not a master) Note that
system errors are reported via the ESC (companion chip)
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