82375EB Datasheet, PDF (77/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
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Figure 15 Access to Locked Target with PLOCK Asserted During Address Phase
5 1 9 DEVICE SELECTION
The PCEB asserts DEVSEL to indicate that it is the target of the PCI transaction DEVSEL is asserted
when the PCEB as a target positively subtractively or negatively (82374SB only) decodes the PCI transac-
tion In all cases except one once the PCEB asserts DEVSEL the signal remains asserted until FRAME is
negated (IRDY is asserted) and either STOP or TRDY is asserted The exception is a target abort
described in Section 5 1 10 Transaction Termination
For most systems PCI target devices are able to complete a decode and assert DEVSEL within 2 or 3
clocks of FRAME (medium and slow in the Figure 16) Accordingly since the PCEB subtractively or nega-
tively (82374SB only) decodes all unclaimed PCI cycles (except configuration cycles) it provides a configura-
tion option to reduce by 1 clock the edge at which it samples DEVSEL allowing faster access to the
expansion bus Use of this option is limited by the slowest positive decode agent on the bus This is described
in more detail in Section 4 0 Address Decoding
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