82375EB Datasheet, PDF (109/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Note that I O recovery is only required for ISA I O devices However since the PCEB does not distinguish
between 8-bit ISA and 8-bit EISA the delay is also applied to 8-bit EISA I O accesses (i e the ESC)
8 0 EISA DATA SWAP BUFFERS
The PCEB contains a set of buffers latches that perform data swapping and data size translations on the EISA
Bus when the master and slave data bus sizes do not match (e g 32-bit EISA master accessing a 16-bit EISA
slave) During a data size translation the PCEB performs one or more of the following operations depending
on the master slave type (PCI EISA ISA) transfer direction (read write) and the number of byte enables
active (BE 3 0 )
 Data assembly or disassembly
 Data copying (up or down)
 Data re-drive
These operations are described in this section An example is provided in Section 8 3 The Re-Drive Opera-
tion that shows a cycle where all three functions are used
The PCEB performs data size translations on the EISA Bus using the data swap buffer control signals generat-
ed by the ESC These signals are described in Section 10 0 PCEB ESC Interface
8 1 Data Assembly And Disassembly
The data assembly disassembly process occurs during PCI EISA ISA and DMA cycles when the master data
size is greater than the slave data size For example if a 32-bit PCI master is performing a 32-bit read cycle to
an 8-bit ISA slave the ESC intervenes and performs four 8-bit reads The data is assembled in the PCEB
(Figure 29) Once assembled the PCEB transfers the data as a single Dword to the 32-bit PCI master during
the fourth cycle For a 32-bit write cycle the PCEB disassembles the Dword by performing four write cycles to
the slave The actual number of cycles required to perform an assembly disassembly process and make a
transfer is a function of the number of bytes (BE 3 0 ) requested and the master slave size combination
During EISA master assembly disassembly transfers cycle control is transferred from the master to the ESC
The master relinquishes control by backing off the bus (i e by floating its START BE 3 0 and SD 31 0
signals on the first falling edge of BCLK after START is negated) The ESC controls the assembly disassem-
bly process in the PCEB via the data swap buffer control signals on the PCEB ESC interface At the end of the
assembly disassembly process cycle control is transferred back to the bus master (by the ESC asserting
EX16 and EX32 ) An additional BCLK is added at the end of the transfer to allow the exchanging of cycle
control to occur During DMA transfers cycle control is maintained by the ESC for the entire cycle
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