82375EB Datasheet, PDF (26/131 Pages) Intel Corporation – PCI-EISA BRIDGE (PCEB)

82375EB SB
Pin Name Type
Description
DATA SWAP BUFFER CONTROL
SDCPYEN01 in
SDCPYEN02
SDCPYEN03
SDCPYEN13
COPY ENABLE These active Low signals perform byte copy operation on the
EISA data bus (SD 31 0 ) The Copy Enable signals are asserted during mis-
matched cycles and are used by the PCEB to enable byte copy operations
between the SD data byte lanes 0 1 2 and 3 as follows
SDCPYEN01
Copy between Byte Lane 0 (SD 7 0 ) and Byte Lane 1
(SD 15 8 )
SDCPYEN02
Copy between Byte Lane 0 (SD 7 0 ) and Byte Lane 2
(SD 23 16 )
SDCPYEN03
Copy between Byte Lane 0 (SD 7 0 ) and Byte Lane 3
(SD 31 24 )
SDCPYEN13
Copy between Byte Lane 1 (SD 15 8 ) and Byte Lane 3
(SD 31 24 )
Note that the direction of the copy is controlled by SDCPYUP
SDCPYUP
in
SYSTEM DATA COPY UP SDCPYUP controls the direction of the byte copy
operation A high on SDCPYUP indicates a COPY UP operation where the lower
byte(s) of the SD data bus are copied onto the higher byte(s) of the bus A low on
the signal indicates a COPY DOWN operation where the higher byte(s) of the data
bus are copied on to the lower byte(s) of the bus The PCEB uses this signal to
perform the actual data byte copy operation during mis-matched cycles
SDOE 2 0
in
SYSTEM DATA OUTPUT ENABLE These active Low signals enable the SD data
output onto the EISA Bus The ESC only activates these signals during mis-
matched cycles The PCEB uses these signal to enable the SD data buffers as
follows
SDOE0
SDOE1
SDOE2
Enables byte lane 0 SD 7 0
Enables byte lane 1 SD 15 8
Enables byte lane 3 SD 31 24 and byte lane 2
SD 23 16
SDLE 3 0
in
SYSTEM DATA LATCH ENABLE SDLE 3 0 enable the latching of data on the
EISA Bus These signals are activated only during mis-matched cycles except
PCEB-initiated write cycles The PCEB uses these signals to latch the SD data bus
as follows
SDLE0
SDLE1
SDLE2
SDLE3
Latch byte lane 0 SD 7 0
Latch byte lane 1 SD 15 8
Latch byte lane 2 SD 23 16
Latch byte lane 3 SD 31 24
2 7 Test Signal
Pin Name Type
Description
TEST
in
TEST This pin is used to tri-state all PCEB outputs During normal operations this pin
must be tied high
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