PXB4219 Datasheet, PDF (98/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

FTDAT[0:7]
FTMFS[0:7]
FTFRS[0:7]
RFCLK
PXB4219 / PXB4220 / PXB4221
Interface Description
10 =
Clock derived from RFCLK
11 =
No clock
Framer Transmit Data
depending on bit “ftri” in “opmo”:
0=
FTDAT is clocked with the falling edge of FTCKO
1=
FTDAT is clocked with the rising edge of FTCKO
Framer Transmit Multiframe Synchronization
Depending on bit p_ces in pcfN:
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Superframe frame mode: FTMFS is asserted
every 12 frames (1.5 ms)
1 = Extended superframe mode: FTMFS is
asserted every 24 frames (3 ms)
1=
Unstructured CES: Inactive level
Depending on bit “tfpp” in “opmo”:
0=
FTMFS is active low
1=
FTMFS is active high
Framer Transmit Frame Synchronization Pulse
FTFRS is asserted synchronously to the transmission of the F-bit
of each frame.
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
Data Sheet
98
2002-05-06