PXB4219 Datasheet, PDF (80/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
During start-up and restart, PLL-ACM will be free running for 8 x tiniN[tini] x T_Data as
programmed in the Time of Initial Free Run Register (“tiniN”, see Chapter 7.54). During
this time the data buffer is filled with an initial number of bytes. As tiniN[tini] is 2 bit longer
than "stav_ini" in the AAL Transmit Reference Slot of RAM3 it is possible to choose a
longer-than-necessary initialization time, to compensate start-up time differences.
After the initial free run, PLL-ACM will start locking in. The lock in time depends on:
• The difference between the initial number of bytes in the data buffer (see “starv_ini” of
the “AAL Transmit Reference Slot” in RAM3) and the value programmed in register
“avbN”.
• The damping, which is influenced by register “asfN”.
• The maximum allowed frequency deviation given by “tur” of register “condN”.
• The required frequency deviation.
During this lock-in process, the output frequency might temporarily reach the
programmed minimum or maximum value. This strongly depends on the initial difference
of the data buffer filling from the value given by “avbN”.
As re-initialization of the data buffer is not reported to the ICRC, PLL-ACM will detect a
huge difference between data buffer filling and the value given by “avbN”. As a result the
output frequency will be driven to it's lowest allowed value and stays there for a relative
long period of time. For this reason it is important to program the field “tur” in register
“condN” with the smallest possible value.
4.5.11.4 SRTS with ACM:
The combination of SRTS and ACM is used when the derived network clock of the SRTS
generator differs from the derived network clock of the SRTS receiver. The maximum
difference is relatively small (+/-4.6 ppm) and should be compensated by ACM. In this
case the shifting of the difference between ACM data and register “avbN”, as
programmed in register “asfN”, has to be reduced. Stable operation of PLL-ACM in
parallel with PLL-SRTS can not be guaranteed if the shifting is not reduced. The cut off
frequency of PLL-ACM has to be much lower than the cut off frequency of PLL-SRTS,
as these PLLs are working in parallel in this case. This will also reduce the effects of
CDV, because the cut off frequency of PLL-ACM is reduced. The tuning range (register
“condN”, field “tur”) can not be reduced as PLL-ACM has to compensate jitter which is
generated by or passed through PLL-SRTS.
Data Sheet
80
2002-05-06