PXB4219 Datasheet, PDF (146/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Memory Structure
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 port_nr
[2:0]
channel_nr
[4:0]
cell_nr double_word 0
[1:0]
[3:0]
6.2.7.1 ATM Receive Buffer
The SW does not need to access the ATM Receive Buffers.
6.2.7.2 Segmentation Buffer
The ATM header to be used for each channel has to be programmed at the address
given by:
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 port_nr[2:0] ref_slot_nr[4:0] 00_B
0000_B
0
All other locations should never be accessed as the data changes continuously.
The format of the ATM header entry in the cell insertion buffer is as follows:
31
24
VCI[3:0]
PTI[2:0]
CLP
23
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
VPI[7:4]
6.2.8 Reassembly/ATM Transmit Buffers
Read/write Address 30000_H to 3FFFF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 32K × 32 bits: 8 ports x 32 channels x 8 cells x 16 doublewords
Data Sheet
146
2002-05-06