PXB4219 Datasheet, PDF (75/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
The frame receiver is synchronized to the received synchronization signal PDSYN by
means of an internal synchronization counter. In case no sync signal is received, frames
are synchronized to the counter. The synchronization between PDSYN and the internal
counter is checked each time PDSYN is received. A synchronization error is indicated
via bit “scri” in the Interrupt Source Register (“irs”, see Chapter 7.44) at the start of a
series of wrong synchronized frames. Synchronization errors are counted and the
internal synchronization counter is synchronized on the new received synchronization
pulse. An errored frame (parity error) is indicated via bit “per” in “irs” but processed as a
normal frame.
In case the internal interface to the ICRC is switched off by the system, SCLK keeps
working. The ICRC detects the following errors:
• Parity error: Because SDOD and SDOR are continuously high, the odd parity is
violated.
• Synchronization error: Because PDSYN is continuously low, synchronization is not
possible.
For ACM, the Reassembly Buffer filling level is measured in number of octets and
passed to the ICRC each time a accepted cell is stored in the Reassembly Buffer.
The arrival time between 2 ACM data values is verified. The assumed maximum CDV is
4 ms. The maximum cell distance without CDV is 0.276 ms for T1 and 0.221 ms for E1.
In case the next ACM data value is not arrived within 10 ms, an error indicated in register
“atlN” is generated.
4.5.4 RTS Receive FIFO
This block is implemented for each port.
The RTS Receive FIFO compensates the Cell Delay Variation (CDV), the delay of the
system interface with it's FIFO and the phase difference between reading and writing of
the RTS Receive FIFO. Each RTS Receive FIFO provides space for 8 RTS values. After
reaching the initial filling level of 5 RTS values, delay variations of +3 / -5 RTS values
can be compensated. This corresponds to a maximum CDV of -4.4 / +7.3 ms (E1) or -
5.8 / +9.7 ms (T1).
In case of overflow (register “sroN”) or underflow (register “sruN”) the PLL-SRTS is put
in free running mode and the FIFO is restarted. These events are indicated in the SRTS
Receive FIFO Underflow Register (sruN, see Chapter 7.60) and the SRTS Receive
FIFO Overflow Register (sroN, see Chapter 7.61).
In case of SRTS the PLL start-up is delayed until 5 RTS values are received. This will
take 7.3 ms for E1 and 9.7 ms for T1. During this time PLL-SRTS is free running (and bit
“frr” of register “statN” is set).
If the PLL block does not use RTS values (bit “srt”=0 in register “condN”) or the port is in
power down mode (bit “pwd”=1 in register “condN”) no data is written to this FIFO. In
Data Sheet
75
2002-05-06