PXB4219 Datasheet, PDF (137/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Memory Structure
6.2
External RAM
The IWE8 requires an external 64K × 32 bit RAM. A 33th bit is added for parity.
MPADR[17:0]
3FFFF_H
30000_H
2FFFF_H
28000_H
27FFF_H
26040_H
2603F_H
26020_H
2601F_H
26000_H
25FFF_H
24000_H
23FFF_H
22000_H
21FFF_H
20000_H
64k × 16
32k × 32
Reassembly / ATM Transmit Buffers
32k × 16
16k × 32
Segmentation / ATM Receive Buffers
8128 x 16
4064 x 32
Cell Extraction Buffer
32 × 16
16 × 32
Cell Insertion Buffer
32 × 16
16 × 32
Timers
8k × 16
4k × 32
Interrupt queue
8k × 16
4k × 32
Statistics Counter thresholds
8k × 16
4k × 32
Statistics Counters
Figure 37 Structure of the IWE8 external RAM
RMADR[15:0]
FFFF_H
8000_H
7FFF_H
4000_H
3FFF_H
3020_H
301F_H
3010_H
300F_H
3000_H
2FFF_H
2000_H
1FFF_H
1000_H
0FFF_H
0000_H
6.2.1 Statistics Counters
Read/write Address 20000_H to 21FFF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 4K × 32 bits: 8 ports x 32 channels x 16 counters.
The statistics counters are incremented when the “channel_mode” is active or standby,
and when the corresponding enable bit in the “catm” or “caal” register is set.
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 port_nr
[2:0]
channel_nr[4:0] counter_nr[3:0] 0
Data Sheet
137
2002-05-06