PXB4219 Datasheet, PDF (22/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Overview
1.3.1 Line Card
Figure 3 shows an example Line Interface Card (LIC) utilizing the IWE8 in a switch
environment. Two Infineon Quad Framer and Line Interface Component (QuadFALC,
PEB 22554) chips are connected at the PCM ports. An ATM Layer circuit is connected
at the UTOPIA Interface port and could be implemented using Infineon PXB 4350 ATM
Layer Processor (ALP) chip.
T1/E1
Lines
Serial
Interface
UTOPIA
Interface
FT SSRAM
64 K x 36 Bit
Switching
Network
Mag.
QuadFALC
PEB 22554
Mag.
QuadFALC
PEB 22554
IWE8
ATM Layer
Circuit
e.g. ALP
PXB 4350
Clock Supply
Clock = 25 MHz
Figure 3 Line Card for 8 T1/E1 Channels
External synchronous SRAM is always required for proper IWE8 operation. The IWE8
requires only one main operating clock of 12 times the datarate of one port. An
emergency clock of 32.768 MHz is optional. The Framer and Utopia interface clocks can
be completely asynchronous with respect to the main clock. A microprocessor controls
and operates the IWE8 via a generic 16-bit interface.
1.3.2 Echo Canceller
In communication links reflections resulting in an electrical echo are due to hybrid splits
or imperfect terminations in subscriber loops. Acoustical echoes may occur due to poor
isolation of microphone and speaker of some telephone systems. These electrical and
acoustical echoes disturb the quality of the transmission. To ensure high quality, pure
data transmission the ITU-T suggests in the recommendation G.131 [22] the use of echo
cancellers. Echo cancellation is extremely desirable for data links with total round trip
transmission times of more than 50 ms.
Data Sheet
22
2002-05-06