PXB4219 Datasheet, PDF (29/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

Table 2
Pin No.
V6
Y9
U7
W2, Y1,
W3, Y2,
W4
PXB4219 / PXB4220 / PXB4221
Pin Descriptions
UTOPIA Interface (36 pins) (cont’d)
Symbol
Input (I) Function
Output (O)
TXCLAV
Slave: O
Master: I
PDA
UTOPIA Transmit Cell Available
Slave: TXCLAV is an active high signal
asserted by the PHY layer to indicate it can
accept data.
Master: TXCLAV is an active high signal
asserted by the ATM layer to indicate it can
accept data.
TXCLK
I
UTOPIA Transmit Clock
Data transfer/synchronization clock
provided by the ATM layer to the PHY layer
for synchronizing transfers on TXDAT[0:7].
TXENB
Slave: I
Master: O
PUA
UTOPIA Transmit Enable
Slave: Active low signal asserted by the
ATM layer during cycles when
TXDAT[0:7] contains valid cell data.
Master: Active low signal asserted by
the PHY layer during cycles when
TXDAT[0:7] contains valid cell data.
TXADR[4:0] I
PUA
UTOPIA Transmit Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to poll and select the
appropriate MPHY device. TXADR4 is the
MSB.
Data Sheet
29
2002-05-06