PXB4219 Datasheet, PDF (15/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Table 42
Table 43
Table 44
Table 45
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY) .
258
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY). .
258
Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) . .
259
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) . . .
259
Clock Recovery Interface AC Timing Characteristics . . . . . . . . . . . . 261
Intel Mode Write Cycle AC Characteristics . . . . . . . . . . . . . . . . . . . . 262
Intel Mode Read Cycle AC Timing Characteristics . . . . . . . . . . . . . . 263
Motorola Mode AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . 264
RAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . 266
Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . 267
Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Bit allocation of channel associated 64 kbit/s time slot 16 for channel as-
sociated signalling 281
Allocation of Channel Associated Signalling Bits to 24 Frame Multiframe.
283
Data Sheet
15
2002-05-06