PXB4219 Datasheet, PDF (121/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Memory Structure
6.1
Internal Configuration RAM’s
The 4 internal 256 x 32 bit configuration RAM’s (RAM1, RAM2, RAM3 and RAM4) are
used to assign the timeslots of the Framer Receive and Framer Transmit interfaces to
ATM channels. For each port there are 32 entries. RAM1 is used to define the timeslots
of the Framer Receive ports, and RAM2 and RAM3 are used to define the Framer
Transmit ports. RAM4 is responsible for CAS conditioning and freezing in transmit
direction
When the contents of the internal RAMs have been altered by the software, the internal
state machines will load the new values within the next 1.5 frame cycles (187.5 µs). Up
to that point of time the previous values are used.
6.1.1 RAM1: Receive Port Configuration
Read/write Address 00200_H to 003FF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 port_nr
[2:0]
slot[4:0]
6.1.1.1 RAM1: ATM Receive Reference Slot
Read/write Address 00200_H to 003FF_H
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
23
15
7
ocd_start ocd_end
_intrpt _intrpt
Not used
Not used
Not used
go_hunt delete_ x43_ channel_mode[1:0]
idle_cells descram
bling
24
16
8
0
ref_slot
=1
Data Sheet
121
2002-05-06