PXB4219 Datasheet, PDF (144/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Memory Structure
MPADR[17:0]
2603B_H
26024_H
26023_H
26022_H
26021_H
26020_H
ATM Cell Payload
Not Used
ATM Header
RMADR[15:0]
301D_H
3012_H
3011_H
3010_H
The ATM header to be used for cell insertion has to be programmed at
MPADR = 26020_H.
The format of the ATM Header entry is as follows:
31
24
VCI[3:0]
PTI[2:0]
CLP
23
16
VCI[11:4]
15
8
VPI[3:0]
VCI[15:12]
7
0
GFC[3:0] or VPI[11:8]
VPI[7:4]
6.2.6 Cell Extraction Buffer
Read/write Address 26040_H to 27FFF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 8127 × 32 bits: 254 cells x 16 doublewords
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10011
cell_nr[7:0] + 2
double_word 0
[3:0]
Data Sheet
144
2002-05-06