PXB4219 Datasheet, PDF (77/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
work properly with these RTS values via bit “pwd” of “condN”. If “srt” in “condN” is reset,
the output of the RTS Receive FIFO is not used by PLL-SRTS.
4.5.8 Fractional Divider
The fractional divider generates a 2.43 MHz clock from the 51.84 MHz clock provided via
the CLK52 pin. This is done by selecting 3 out of 64 clock pulses of 51.84 MHz. The
resulting 2.43 MHz clock contains jitter components of 810 kHz and above, with a
maximum peak to peak jitter of 19 ns.
4.5.9 Clocks
For an overview on the required clocks for the ICRC please refer to Chapter 8.1.
4.5.10 Power Management
Different Power down modes are available for the ICRC:
• for each port via bit “pwd” in “condN”
• for the Clock Recovery Interface via bit “pdcri” in “icrcconf”.
• for the complete ICRC by means of the “a_icrc_dwn” bit in the “acfg”. This feature
reduces the power consumption by approximately 50 mW. Once the ICRC is switched
off, it can only be enabled by hardware reset of the whole device.
4.5.11 PLL Block
This block is implemented for each port. It consists of 3 PLLs: PLL-SRTS, PLL-ACM and
PLL-FILTER.
The bits “srt” and “acm” in the register “condN” define, which PLL is connected to PLL-
FILTER and used for clock recovery. Each PLL may be used exclusively or in
combination.
4.5.11.1 PLL-SRTS:
PLL-SRTS is used for clock recovery using the SRTS method. It has a cut-off frequency
of 20 to 50 Hz.
The phase detector of PLL-SRTS has a linear range which optimized for jitter tolerance
requirements. It is defined by a “window” of accepted RTS values. Each time PLL-SRTS
detects values, which fall out of the window, or processes invalid values, it is forced in
hold over for 1 SRTS period, bit “hov” of register “statN” is set and the
SRTS Invalid Value Processed Counter (“sriN”, see Chapter 7.63) is incremented. In
case the number of out of window conditions during 16 SRTS periods exceeds the value
given by field “tr_srts” of register “treshN”, an out of lock message, indicated with bit “ols”
of register “oolN” is generated. During start-up of the RTS Receive FIFO, PLL-SRTS is
free running and bit “frr” of register “statN” is set.
Data Sheet
77
2002-05-06