PXB4219 Datasheet, PDF (78/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
4.5.11.2 PLL-FILTER
The PLL “PLL-FILTER” has a very low cut off frequency and a tuning range of +/ -240
ppm. It reduces jitter which is generated in, or passed through PLL-SRTS. Although PLL-
FILTER is placed behind PLL-ACM, it has little or no functionality in case of ACM, as
PLL-ACM has a lower cut off frequency.
If more out of lock detections during 16 SRTS periods are detected than defined with
“tr_filt” in “tresh”, an out of lock message, indicated by bit “olf” of register “oolN”, is
generated.
4.5.11.3 PLL-ACM
The PLL-ACM is a control system with feedback of 2nd order. Its phase is adjusted
according to the filling level of the Reassembly Buffer.
The average buffer filling level as defined in bits “avb” in the Average Buffer Filling
Register (“avbN”, see Chapter 7.52) is subtracted from the current buffer filling level.
The result is amplified in order to adjust the cut off frequency and to define the system’s
damping (number of bytes, needed to drive the DCO over its tuning range. The loop gain
is programmed in the ACM Shift Factor Register (asfN, see Chapter 7.53). Although
adjustable, the PLL-cut-off frequency is generally less than 1 Hz. In conjunction with a
low pass filter, CDV is very small.
The behaviour of the PLL is characterized by rise time and lock in time. The rise time is
the time when the clock output enters the predefined tuning range for the first time. The
lock in time is defined as the time after which the clock stays within the accepted
deviation.
f/f₀
2d
Mp
1
0.9
0.1
Figure 20
Tr1 Tr Tp
Transient Parameters
Tr, Tr1: Rise time
Tp: Peak time
Tl: Lock in time
Mp: Peak overshoot
2d: Tuning range
f₀:
Target frequency
Tl
t
Data Sheet
78
2002-05-06