PXB4219 Datasheet, PDF (257/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
The setup and the hold times are defined with regard to a positive clock edge, see
Figure 64.
Taking the actual used clock frequency into account (e.g. up to the max. frequency), the
corresponding (min. and max.) transmit side “clock to output” propagation delay
specifications can be derived. The timing references (tT5 to tT12) are according
toTable 42 to Table 45.
In the following tables, A>P (column DIR, Direction) defines a signal from the ATM layer
(transmitter, driver) to the PHY layer (receiver), A<P defines a signal from the PHY layer
(transmitter, driver) to the ATM layer (receiver).
Clock
Signal
Figure 64
tT5, tT7
tT6, tT8
input setup to clock input hold from clock
Setup and hold time definition (single- and multi PHY)
Clock
tT9
tT10
Signal
Figure 65
tT11
tT12
signal going low
impedance from clock
signal going low
impedance to clock
signal going high signal going high
impedance from clock impedance to clock
Tri-state timing (multi-PHY, multiple devices only)
Data Sheet
257
2002-05-06