PXB4219 Datasheet, PDF (94/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Interface Description
The data is transferred between the FALC and the IWE8 via a system internal highway.
FRCLK[0:7]
FRDAT[0:7]
FRMFB[0:7]
FRFRS[0:7]
FRLOS[0:7]
FTCKO[0:7]
FTDAT[0:7]
FTMFS[0:7]
Framer Receive Clock
Receive system clock of 8.192 MHz (falling)
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of FRCLK
Framer Receive Multiframe Begin
Depending on bits “p_ces” in “pcfN”:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused
FRMFB is always sampled with the falling edge of FRCLK.
Framer Receive Frame Synchronization Pulse
FRFRS is generated at the beginning of timslot0 of each frame
Framer Receive Loss of Signalling
Framer Transmit Clock
depending on bits ftckn in ftcs:
00 =
depending on bit “rts_eval” in “opmo”:
0 = Transmit clock input with 8.192 MHz (falling)
1 = Clock of ICRC is used as transmit clock and is
also switched to FTCKO pins (FTCKO is output
pin)
01 =
FRCLK
10 =
Clock derived from RFCLK
11 =
No clock
Framer Transmit Data
FTDAT is clocked with the falling edge of FTCKO:
Framer Transmit Multiframe Synchronization
Depending on bit p_ces in pcfN:
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1 = CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms)
1=
Unstructured CES: Unused, constant low level
Data Sheet
94
2002-05-06