PXB4219 Datasheet, PDF (154/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Register Description
7.2
ASIC Configuration Register (acfg)
Read/write Address 00008_H
Reset value: 0000_H
15
a_icrc_
dwn
a_hec_ a_hec_
algor mode
7
a_dummy_rts[2:0]
a_sw_
reset
a_ut_en
a_emg_bpslct[1:0]
8
a_ur_en
a_crv_en
a_dummy
_rts[3]
0
a_ovf_ a_ptr_ a_even_
cnt_en prty
pck
a_icrc_dwn ICRC power down
Once the SRTS block is switched off, it can only be enabled by hardware
reset of the whole device.
0 = Enabled
1 = Disabled
a_hec_algor HEC detection, correction
0 = HEC algorithm according to ITU-T
1 = HEC algorithm according to ATM Forum
a_hec_
mode
Handling in case of faulty HEC
0 = Standard mode:
Cell discard upon detection of uncorrectable HEC error
1 = as defined in pcfN.p_cell_disc
a_sw_reset
Software reset
Reset registers 0000_H to 0031_H including this bit.
0 = Normal
1 = Reset
a_ut_en
UTOPIA transmit enable
0 = Disabled
1 = Enabled
a_ur_en
UTOPIA receive enable
0 = Disabled
1 = Enabled
Data Sheet
154
2002-05-06