PXB4219 Datasheet, PDF (46/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
pressure state. This results in two side effects, which have to be taken into account for
the calculation of threshold values.
• After back pressure state has been entered, up to 8 additional cells may be transferred
from the UTOPIA input buffer to the port buffer.
• Before a certain cell can cause port specific back pressure, it has to traverse the
UTOPIA input buffer, resulting in a delay of 4.2 to 16.8 µs.
4.1.1.2 Cell Discarding
The discarding of cells is available for ATM ports. It can depend on
• Buffer filling level and CLP (Bit 0 of the 4th ATM header octet)
• Buffer filling level and CLPI (Cell Loss Priority Internal, bit 6 of the UDF octet at the
UTOPIA interface)
The bit ENB, bit 5 of the UDF octet at the UTOPIA interface, is responsible for the
decision if discarding shall base on CLP or CLPI. For bit locations see Figure 30.
The buffer threshold for discarding cells is configured by register “thrshld” and applies to
all ports.
Cells that are going to be extracted via the microprocessor interface will be ignored by
the cell discard mechanism
Table 12 ATM Cell Discarding
ENB CLPI CLP Discarding
0
x
0
No
0
x
1
Yes, if buffer threshold has been exceeded
1
0
x
No
1
1
x
Yes, if buffer threshold has been exceeded
4.1.1.3 Cell rate de-coupling: Idle/Unassigned Cell Insertion
When the ATM Transmit Buffer of a port is empty, idle or unassigned cells are
transmitted to provide cell rate de-coupling.
Idle cells are transmitted as defined in the ITU-T I.361 [30]. Unassigned cells can be
inserted, as defined in the B-ISDN UNI and NNI physical layer generic criteria [15].
The 4 MSBs of header octet 1 and the 4 LSBs of header octet 4 are programmable in
the “prg_tx_hd” field of the TX Idle/Unassigned Cell Control Register (txid, see
Chapter 7.10). All other header bits will be 0.
Data Sheet
46
2002-05-06