PXB4219 Datasheet, PDF (12/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
List of Figures
Page
Figure 1
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 2
Typical IWE8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3
Line Card for 8 T1/E1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4
Echo Canceller Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 7
Cell delineation state diagram (Figure 5/I.432.1) . . . . . . . . . . . . . . . . . 50
Figure 8
Maintenance state transition diagram for cell delineation events (Figure 2/
I.432.3) 50
Figure 9
HEC: Receiver mode of Operation (Figure 3/ITU I.432.1) . . . . . . . . . . 51
Figure 10 HEC Detection According to ATM Forum . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11 Pre-assigned cell header values at the UNI for use by the physical layer
(excluding the HEC field) (Table 1/I.361) 53
Figure 12 Pre-defined header field values [11] . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13 SAR-PDU of AAL Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14 Synchronization of SRTS Generation with the Start of Segmentation . 60
Figure 15 Reassembly Buffer Initialization: No CDV . . . . . . . . . . . . . . . . . . . . . . 67
Figure 16 Reassembly Buffer Initialization: positive CDV at Start Up . . . . . . . . . 68
Figure 17 Reassembly Buffer Initialization: Negative CDV at Start Up . . . . . . . . 69
Figure 18 Reassembly Buffer Initialization for structured CES: positive CDV at Start
Up 70
Figure 19 Block Diagram of the ICRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 20 Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 21 Influence of Damping on Lock in Time. . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 22 Connection of IWE8 to QuadFALC . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 23 Framer Interface in FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 24 Framer Interface in GIM T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 25 Framer Interface in GIM E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 26 Framer Interface in SYM2 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 27 Framer Interface in SYM8 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 28 Framer Interface in EC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 29 UTOPIA Receive and Transmit Interfaces in Slave Mode . . . . . . . . . 107
Figure 30 Utopia Sideband Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 31 IMA Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 32 Connection of IWE8 to an Intel Type Microprocessor . . . . . . . . . . . . 115
Figure 33 Connection of IWE8 to an Motorola Type Microprocessor . . . . . . . . 116
Figure 34 External RAM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 35 RAM Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 36 Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 37 Structure of the IWE8 external RAM . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 38 Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 39 ACM Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . . 230
Data Sheet
12
2002-05-06