PXB4219 Datasheet, PDF (19/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Overview
– Internal clock recovery circuit using Synchronous Residual Time Stamp (SRTS) or
Adaptive Clock Method (ACM) for unstructured CES ports. For SRTS a patent fee
needs to be paid. Optionally, it’s possible to order the PXB 4221 device, which
comes without SRTS clock recovery.
– Trunk freezing and conditioning according to Bellcore TR-NWT-000170 [14]
• IMA interface:
– Programmable threshold between read and write pointer of Mapping Buffer
– Output Signal for buffer threshold crossing
– Output Signal for discarded cell
– Output pins for port number indication
• 8 generic framer interfaces with integrated transmit clock selector supporting
– Synchronous Mode (SYM)
– Generic Interface Mode (GIM)
– FALC Mode (FAM): Glue-less interface for Infineon’s Framer and Line Interface
Components (FALC)
– Echo Canceller Mode (EC): ATM cells are duplicated internally and transmitted via
two framer ports
• UTOPIA industry standard interface:
– Level 2 in slave mode; 8 data, 5 address lines
– Level 1 in master/slave mode
– UTOPIA clock up to 38.88 MHz
• 16-bit generic microprocessor interface for control and configuration of the chip runs
either in Intel 386EX or Motorola compatible mode
• External synchronous Flow-Through SSRAM 1 x 64K x 33 bit or 1 x 64K x 32 bit
required
• Build-in data path loops for test
• Cell insertion/extraxtion via microprocessor interface
• 3.3 Volt power supply with 5 Volt tolerant inputs
• Typical power dissipation 1 Watt
• P-BGA 256 package
• Temperature range from -40° to +85°C
Data Sheet
19
2002-05-06