PXB4219 Datasheet, PDF (204/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Register Description
7.47
Configuration Register Downstream of Port N (condN)
Read/Write Address 00104_H + N x 32
Reset value: 0840_H
15
8
not used
tur[5:1]
7
0
tur(0]
pwd
lgc
lc8
lgs
lpcr
srt
acm
tur
pwd
lgc
lc8
lgs
lpcr
srt, acm
Tuning range select of port N
The tuning range of PLL-ACM is limited to:
(frequency deviation of pin RFCLK in ppm) +/- ((4*tur) +/-5%)ppm.
Power down of port N
0 = Normal operation
1 = Power down mode. No RTS values and no transmit clock are
generated.
Loop back generated clock
0 = Normal operation
1 = The clock generated by the PLL is looped into the RTS generator.
Loop back clock 8.192 MHz
0 = Normal operation
1 = The receive clock is looped to the transmit output of the ICRC.
Loop back generated RTS
0 = Normal operation
1 = Generated RTS values are looped into the SRTS Receive FIFO.
Loop back clock recovery Interface
0 = Normal operation
1 = The clock recovery interface is bypassed. RTS values from the
frame receiver are looped into the SRTS Transmit FIFO.
Selectors for the clock generation algorithm
00 =
The PLL is put in power down mode, and a free running clock is
generated. In case pwd is set, all circuits of the port, including the
RTS generator are disabled, no output clock is generated and all
error counters are reset.
Data Sheet
204
2002-05-06