PXB4219 Datasheet, PDF (76/290 Pages) Infineon Technologies AG – IWE8 Interworking Element for 8 E1/T1 Lines

PXB4219 / PXB4220 / PXB4221
Operational Description
case bit “ena” of register “tsinN” is set, a value from the SRTS Receive FIFO is read by
reading register “tsout”.
In cases where the network clocks of RTS generator and RTS receiver have a frequency
offset, the SRTS algorithm will generate a service frequency with the same frequency
offset. The rate of RTS value generation and consumption depends on the service
clocks. In this special case, the rate of RTS value consumption is different from the rate
of RTS value generation. Enabling the ACM algorithm will not help as the FIFO is read
by the clock generated by PLL-SRTS. As a result the SRTS Receive FIFO will generate
regular (every 20 minutes) under- or overflows.
4.5.5 RTS Transmit FIFO
Each RTS generator stores the RTS value and its port number in the RTS Transmit
FIFO. When the frame generator starts generating a new frame, it reads from the FIFO
the source address and the next RTS value.
4.5.6 ICRC Loopback Modes
Loopbacks are available for each port and for the system interface of the circuit.
Each port has 2 loopbacks. The first, situated near the framer, performs a loopback on
the clock signals. It is controlled by the bit “lgc” in the Configuration Register
Downstream Direction of Port N (condN, see Chapter 7.47), which sends the generated
clock back to the RTS generator, and “lc8” in “condN”, which sends the received clock
back to the framer interface. The second has the same internal structure. It allows to
send received RTS values of all ports back to the RTS Transmit FIFO (“lpcr”=1 in register
“condN”). Thus, this loop has a variable delay with a guaranteed maximum of RTS
Transmit FIFO depth x Frame-period. If “lgs”=1 in register “condN”, generated RTS
values are sent via the receive FIFO to the PLL.
Another loopback block is situated at the clock recovery interface. It is controlled by the
bits “lptd”, “lptu”, “lprd” and “lpru” in the ICRC configuration register “icrcconf”. Not all loop
back possibilities of this block carry useful data, but the parity can always be tested.
4.5.7 RTS Injection
In case bit “ena” of the Test Input of Port N register (tsinN, see Chapter 7.50) is set, the
RTS Transmit FIFO receives a new RTS value from field “rtsi” of “tsinN” at the moment
the microprocessor writes data to that register. RTS values coming from the RTS
generator of port N are ignored in this case. RTS values coming from the clock recovery
interface and which have to be returned because of loopback “lpcr”, have priority over
register “tsinN”.
During this test, the clock recovery or, in case of loopback, the receive FIFO receives the
RTS values written in field rtsi. It is advisable to power down the circuit(s) which do not
Data Sheet
76
2002-05-06